It is known that carrier (electron or hole) mobility and flow, as well as drive current and other electrical properties, of semiconductor devices, such as FETs or other transistors, are influenced by mechanical compressive and tensile stresses. For example, electron mobility in one or more directions within bulk or SOI silicon that is under uniaxial or biaxial tensile stress is enhanced, while hole mobility is degraded. Similarly, if the silicon is under uniaxial or biaxial compressive stress, hole mobility in one or more directions is enhanced, but electron mobility is degraded.
Uniaxial and biaxial compressive and tensile stresses in the channel of a FET are known to be produced by shallow trench isolation, silicon nitride etch-stops, silicide contacts, epitaxial layers on the substrate and on the etch-stop layer, and other artifacts of fabrication. While these stresses have been analyzed and their causes investigated, precise control thereof to achieve selective and controlled enhancement or degradation of carrier mobility has been somewhat elusive. Some techniques for producing beneficial stress have been developed, but various factors, such as cost, scalability and fabrication integration have so far led to limited adoption of these techniques.